This invention relates to a memory having variable levels of interleaving and a corresponding configurator circuit.
It is known that, in modem data processing systems, the working memory constitutes a "bottleneck" limitation to the system.
In fact, while various processors can operate with very short operation cycles on the order of tens of nsec, the working memories currently in use, which are of the DRAM type for cost reasons, are inherently slower, and the read/write time may be on the order of hundreds of nsec.
Each storage cycle requires a selection operation for the memory location to be read or written, and the selection operation becomes slower and more complex as the size or capacity of the memory increases.